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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) and xdcp are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners single, 128-taps low voltage digitally controlled potentiometer (xdcp?) isl23318 the isl23318 is a volatile, low voltage, low noise, low power, i 2 c bus?, 128 taps, single digitally controlled potentiometer (dcp), which integrates dcp co re, wiper switches and control logic on a monolithic cmos integrated circuit. the digitally controlled potent iometer is implemented with a combination of resistor elements and cmos switches. the position of the wipers are cont rolled by the user through the i 2 c bus interface. the potentiometer has an associated volatile wiper register (wr) that can be directly written to and read by the user. the contents of the wr controls the position of the wiper. when powered on, the isl23318?s wiper will always commence at mid-scale (64 tap position). the low voltage, low power consumption, and small package of the isl23318 make it an ideal choice for use in battery operated equipment. in addition, the isl23318 has a v logic pin allowing down to 1.2v bus operation, independent from the v cc value. this allows for low logic levels to be connected directly to the isl23318 without passing through a voltage level shifter. the dcp can be used as a three- terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ?128 resistor taps ?i 2 c serial interface - no additional level translator for low bus supply - two address pins allow up to four devices per bus ?power supply -v cc = 1.7v to 5.5v analog power supply -v logic = 1.2v to 5.5v i 2 c bus/logic power supply ? wiper resistance: 70 ? typical @ v cc = 3.3v ? shutdown mode - forces the dcp into an end-to-end open circuit and r w is shorted to r l internally ? power-on preset to mid-scale (64 tap position) ? shutdown and standby current <2.8a max ? dcp terminal voltage from 0v to v cc ?10k ? , 50k ? or 100k ? total resistance ? extended industrial temperature range: -40 c to +125 c ? 10 ld msop or 10 ld utqfn packages ? pb-free (rohs compliant) applications ? gain adjustment in battery powered instruments ? trimming sensor circuits ? power supply margining ? rf power amplifier bias compensation figure 1. forward and back ward resistance vs tap position, 10k dcp figure 2. v ref adjustment 0 2000 4000 6000 8000 10000 0326496128 tap position (decimal) resistance ( ? ) v ref_m isl28114 isl23318 + - v ref rl rw rh july 26, 2011 fn7887.0
isl23318 2 fn7887.0 july 26, 2011 block diagram level shifter v cc r h gnd r l r w scl sda a1 a0 power-up interface, control and status logic wr volatile register and wiper control circuitry v logic i/o block pin configurations isl23318 (10 ld msop) top view isl23318 (10 ld utqfn) top view 1 2 3 4 5 6 10 9 8 7 sda v logic a1 a0 gnd scl rl rw rh v cc 9 8 7 6 1 2 3 4 rl a1 v cc rh gnd scl a0 5 10 sda rw v logic pin descriptions msop utqfn symbol description 110v logic i 2 c bus /logic supply. range 1.2v to 5.5v 2 1 scl logic pin - serial bus clock input 3 2 sda logic pin - serial bus data input/open drain output 4 3 a0 logic pin - hardwire slave address pin for i 2 c serial bus. range: v logic or gnd 5 4 a1 logic pin - hardwire slave address pin for i 2 c serial bus. range: v logic or gnd 6 5 rl dcp ?low? terminal 7 6 rw dcp wiper terminal 8 7 rh dcp ?high? terminal 98 v cc analog power supply. range 1.7v to 5.5v 10 9 gnd ground pin
isl23318 3 fn7887.0 july 26, 2011 ordering information part number (note 5) part marking resistance option (k ? ) temp range (c) package (pb-free) pkg. dwg. # isl23318tfuz (notes 1, 3) 3318t 100 -40 to +125 10 ld msop m10.118 isl23318ufuz (notes 1, 3) 3318u 50 -40 to +125 10 ld msop m10.118 isl23318wfuz (notes 1, 3) 3318w 10 -40 to +125 10 ld msop m10.118 isl23318tfruz-t7a (notes 2, 4) hh 100 -40 to +125 10 ld 2.1x1.6 utqfn l10.2.1x1.6a isl23318tfruz-tk (notes 2, 4) hh 100 -40 to +125 10 ld 2.1x1.6 utqfn l10.2.1x1.6a isl23318ufruz-t7a (notes 2, 4) hg 50 -40 to +125 10 ld 2.1x1.6 utqfn l10.2.1x1.6a ISL23318UFRUZ-TK (notes 2, 4) hg 50 -40 to +125 10 ld 2.1x1.6 utqfn l10.2.1x1.6a isl23318wfruz-t7a (notes 2, 4) hf 10 -40 to +125 10 ld 2.1x1.6 utqfn l10.2.1x1.6a isl23318wfruz-tk (notes 2, 4) hf 10 -40 to +125 10 ld 2.1x1.6 utqfn l10.2.1x1.6a notes: 1. add "-tk" or "-t7a" suffix for tape and reel option. please refer to tb347 for details on reel specifications. 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materials and nipdau plate-e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl23318 . for more information on msl please see techbrief tb363 .
isl23318 4 fn7887.0 july 26, 2011 absolute maximum rating s thermal information supply voltage range v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v v logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on any dcp terminal pin . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on any digital pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v wiper current i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . .6.5kv cdm model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . . . . . . . . 1kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v latch up (tested per jesd-78b; class 2, level a) . . . . 100ma @ +125c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld msop package (notes 6, 7) . . . . . . . 170 70 10 ld utqfn package (notes 6, 7) . . . . . . 145 90 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7v to 5.5v v logic supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2v to 5.5v dcp terminal voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to v cc max wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is the center top of the package. analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operat ing conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units r total r h to r l resistance w option 10 k ? u option 50 k ? t option 100 k ? r h to r l resistance tolerance -20 2 +20 % end-to-end temperature coefficient w option 175 ppm/c u option 85 ppm/c t option 70 ppm/c v rh , v rl dcp terminal voltage v rh or v rl to gnd 0v cc v r w wiper resistance r h - floating, v rl = 0v, force i w current to the wiper, i w = (v cc - v rl )/r total, v cc = 2.7v to 5.5v 70 200 ? v cc = 1.7v 580 ? c h /c l /c w terminal capacitance see ?dcp macro model? on page 8 32 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to v cc -0.4 <0.1 0.4 a noise resistor noise density wiper at middle point, w option 16 nv/ hz wiper at middle point, u option 49 nv/ hz wiper at middle point, t option 61 nv/ hz feed thru digital feed-through from bus to wiper wiper at middle point -65 db psrr power supply reject ratio wiper output change if v cc change 10%; wiper at middle point -75 db
isl23318 5 fn7887.0 july 26, 2011 voltage divider mode (0v @ rl; v cc @ rh; measured at rw, unloaded) inl (note 13) integral non-linearity, guaranteed monotonic w, u, t options -0.5 0.15 +0.5 lsb (note 9) dnl (note 12) differential non-linearity, guaranteed monotonic w, u, t options -0.5 0.15 +0.5 lsb (note 9) fserror (note 11) full-scale error w option -2.5 -1.5 0 lsb (note 9) u, t option -1.0 -0.7 0 lsb (note 9) zserror (note 10) zero-scale error w option 0 1.5 2.5 lsb (note 9) u, t option 0 0.7 1.0 lsb (note 9) tc v (notes 14) ratiometric temperature coefficient w opti on, wiper register set to 40 hex 8 ppm/c u option, wiper register set to 40 hex 4 ppm/c t option, wiper register set to 40 hex 2.3 ppm/c large signal wiper settling time from code 0 to 7f hex 300 ns f cutoff -3db cutoff frequency wiper at middle point w option 1200 khz wiper at middle point u option 250 khz wiper at middle point t option 120 khz rheostat mode (measurements between rw and rl pins with rh not connected, or between rw and rh with rl not connected) r inl (note 18) integral non-linearity, guaranteed monotonic w option; v cc = 2.7v to 5.5v -1.0 0.5 +1.0 mi (note 15) w option; v cc = 1.7v 3.0 mi (note 15) u, t option; v cc = 2.7v to 5.5v -0.5 0.15 +0.5 mi (note 15) u, t option; v cc = 1.7v 1.0 mi (note 15) r dnl (note 17) differential non-linearity, guaranteed monotonic w option; v cc = 2.7v to 5.5v -0.5 0.15 +0.5 mi (note 15) w option; v cc = 1.7v 0.4 mi (note 15) u, t option; v cc = 2.7v to 5.5v -0.5 0.15 +0.5 mi (note 15) u, t option; v cc = 1.7v 0.4 mi (note 15) r offset (note 16) offset, wiper at 0 position w option; v cc = 2.7v to 5.5v 0 1.8 3.0 mi (note 15) w option; v cc = 1.7v 3.0 mi (note 15) u, t option; v cc = 2.7v to 5.5v 0 0.3 1 mi (note 15) u, t option; v cc = 1.7v 0.5 mi (note 15) analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operat ing conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units
isl23318 6 fn7887.0 july 26, 2011 tcr (note 19) resistance temperature coefficient w option; wiper register set between 19 hex and 7f hex 220 ppm/c u option; wiper register set between 19 hex and 7f hex 100 ppm/c t option; wiper register set between 19 hex and 7f hex 75 ppm/c analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operat ing conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units operating specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operat ing conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units i logic v logic supply current (write/read) v logic = 5.5v, v cc = 5.5v, f scl = 400khz (for i 2 c active read and write) 200 a v logic = 1.2v, v cc = 1.7v, f scl = 400khz (for i 2 c active read and write) 5 a i cc v cc supply current (write/read) v logic = 5.5v, v cc = 5.5v 18 a v logic = 1.2v, v cc = 1.7v 10 a i logic sb v logic standby current v logic = v cc = 5.5v, i 2 c interface in standby 1.3 a v logic = 1.2v, v cc = 1.7v, i 2 c interface in standby 0.4 a i cc sb v cc standby current v logic = v cc = 5.5v, i 2 c interface in standby 1.5 a v logic = 1.2v, v cc = 1.7v, i 2 c interface in standby 1 a i logic shdn v logic shutdown current v logic = v cc = 5.5v, i 2 c interface in standby 1.3 a v logic = 1.2v, v cc = 1.7v, i 2 c interface in standby 0.4 a i cc shdn v cc shutdown current v logic = v cc = 5.5v, i 2 c interface in standby 1.5 a v logic = 1.2v, v cc = 1.7v, i 2 c interface in standby 1 a i lkgdig leakage current, at pins a0, a1, sda, scl voltage at pin from gnd to v logic -0.4 <0.1 0.4 a t dcp wiper response time scl rising edge of the acknowledge bit after data byte to wiper new position 1.5 s tshdnrec dcp recall time from shutdown mode scl rising edge of the acknowledge bit after acr data byte to wiper recalled position and rh connection 1.5 s v cc, v logic ramp (note 21) v cc , v logic ramp rate ramp monotonic at any level 0.01 50 v/ms
isl23318 7 fn7887.0 july 26, 2011 serial interface specification for scl, sda, a0, a1 unless otherwise noted. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units v il input low voltage -0.3 0.3 x v logic v v ih input high voltage 0.7 x v logic v logic + 0.3 v hysteresis sda and scl input buffer hysteresis v logic > 2v 0.05 x v logic v v logic < 2v 0.1 x v logic v ol sda output buffer low voltage i ol = 3ma, v logic > 2v 0 0.4 v i ol = 1.5ma, v logic < 2v 0.2 x v logic v c pin sda, scl pin capacitance 10 pf f scl scl frequency 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v logic , until sda exits the 30% to 70% of v logic window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v logic during a stop condition, to sda crossing 70% of v logic during the following start condition 1300 ns t low clock low time measured at the 30% of v logic crossing 1300 ns t high clock high time measured at the 70% of v logic crossing 600 ns t su:sta start condition set-up time scl rising edge to sda falling edge; both crossing 70% of v logic 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v logic to scl falling edge crossing 70% of v logic 600 ns t su:dat input data set-up time from sda exiting the 30% to 70% of v logic window, to scl rising edge crossing 30% of v logic 100 ns t hd:dat input data hold time from scl falling edge crossing 70% of v cc to sda entering the 30% to 70% of v logic window 0ns t su:sto stop condition set-up time from scl rising edge crossing 70% of v logic , to sda rising edge crossing 30% of v logic 600 ns t hd:sto stop condition hold time for read or write from sda rising edge to scl falling edge; both crossing 70% of v logic 1300 ns t dh output data hold time from scl falling edge crossing 30% of v logic , until sda enters the 30% to 70% of v logic window. i ol =3ma,v logic > 2v. i ol = 0.5ma, v logic < 2v 0ns t r sda and scl rise time from 30% to 70% of v logic 20 + 0.1 x cb 250 ns
isl23318 8 fn7887.0 july 26, 2011 dcp macro model t f sda and scl fall time from 70% to 30% of v logic 20 + 0.1 x cb 250 ns cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf t su:a a1, a0 set-up time before start condition 600 ns t hd:a a1, a0 hold time after stop condition 600 ns notes: 8. typical values are for t a = +25c and 3.3v supply voltages. 9. lsb = [v(rw) 127 ? v(rw) 0 ] / 127. v(rw) 127 and v(rw) 0 are v(rw) for the dcp register set to 7f hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 10. zs error = v(rw) 0 / lsb. 11. fs error = [v(rw) 127 ? v cc ] / lsb. 12. dnl = [v(rw) i ? v(rw) i-1 ] / lsb-1, for i = 1 to 127. i is the dcp register setting. 13. inl = [v(rw) i ? i ? lsb ? v(rw) 0 ]/lsb for i = 1 to 127. 14. for i = 16 to 127 decimal, t = -40c to +125c. max( ) is the maximum value of the wiper voltage and min( ) is the minimum value of the wiper voltage over the temperature range. 15. mi = | rw 127 ? rw 0 | / 127. mi is a minimum increment. rw 127 and rw 0 are the measured resistances for the dcp register set to 7f hex and 00 hex respectively. 16. roffset = rw 0 / mi, when measuring between rw and rl. roffset = rw 127 / mi, when measuring between rw and rh. 17. rdnl = (rw i ? rw i-1 ) / mi -1, for i = 8 to 127. 18. rinl = [rw i ? (mi ? i) ? rw 0 ] / mi, for i = 8 to 127. 19. for i = 8 to 127, t = -40c to +125c. max( ) is th e maximum value of the resi stance and min( ) is the minimum value of the resistance over the temperature range. 20. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 21. it is preferable to ramp up both the v logic and the v cc supplies at the same time. if this is not possible, it is recommended to ramp-up the v logic first followed by the v cc . serial interface specification for scl, sda, a0, a1 unless otherwise noted. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units tc v max v rw () i () min v rw () i () ? vrw i +25c () () ----------------------------------------------------------------------------- - 10 6 +165c --------------------- = tc r max ri () min ri () ? [] ri +25c () ------------------------------------------------------ - 10 6 +165c --------------------- = 32pf rh r total c h 32pf c w c l 32pf rw rl
isl23318 9 fn7887.0 july 26, 2011 timing diagrams sda vs scl timing a0 and a1 pin timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t sp t hd:a scl sda a0, a1 t su:a clk 1 start stop typical performance curves figure 3. 10k dnl vs tap position, v cc = 5v figure 4. 50k dnl vs tap position, v cc = 5v -0.4 -0.2 0 0.2 0.4 0 163248648096112128 d n l ( ls b ) tap position (decimal) -0.04 -0.02 0 0.02 0.04 0 163248648096112128 d n l ( ls b ) tap position (decimal)
isl23318 10 fn7887.0 july 26, 2011 figure 5. 10k inl vs tap position, v cc = 5v figure 6. 50k inl vs tap position, v cc = 5v figure 7. 10k rdnl vs tap position, v cc = 5v figure 8. 50k rdnl vs tap position, v cc = 5v figure 9. 10k rinl vs tap position, v cc = 5v figure 10. 50k rinl vs tap position, v cc = 5v typical performance curves (continued) -0.4 -0.2 0 0.2 0.4 0 16 32 48 64 80 96 112 128 i n l ( l s b ) tap position (decimal) -0.16 -0.08 0 0.08 0.16 0 16 32 48 64 80 96 112 128 i n l ( l s b ) tap position (decimal) -0.4 -0.2 0 0.2 0.4 0 163248648096112128 rdnl (mi) tap position (decimal) -0.10 -0.05 0 0.05 0.10 0 163248648096112128 r d n l ( m i ) tap position (decimal) -0.4 -0.2 0 0.2 0.4 0 163248648096112128 r i n l ( m i ) tap position (decimal) -0.16 -0.08 0 0.08 0.16 0 163248648096112128 r i n l ( m i ) tap position (decimal)
isl23318 11 fn7887.0 july 26, 2011 figure 11. 10k wiper resistance vs tap position, v cc = 5v figure 12. 50k wiper resistance vs tap position, v cc = 5v figure 13. 10k tcv vs tap position figure 14. 50k tcv vs tap position figure 15. 10k tcr vs tap position figure 16. 50k tcr vs tap position typical performance curves (continued) 0 10 20 30 40 50 60 0 163248648096112128 w i p e r r e s i s t a n c e ( ? ) tap position (decimal) +125c -40c +25c 0 10 20 30 40 50 0 163248648096112128 w i p e r r e s i s t a n c e ( ? ) tap position (decimal) +125c -40c +25c 0 20 40 60 80 100 120 140 16 32 48 64 80 96 112 128 t c v ( p p m / c ) tap position (decimal) 0 5 10 15 20 25 30 16 32 48 64 80 96 112 128 t c v ( p p m / c ) tap position (decimal) 0 50 100 150 200 250 300 350 16 32 48 64 80 96 112 128 t c r ( p p m / c ) tap position (decimal) 0 25 50 75 100 16 32 48 64 80 96 112 128 t c r ( p p m / c ) tap position (decimal)
isl23318 12 fn7887.0 july 26, 2011 figure 17. 100k tcv vs tap position figure 18. 100k tcr vs tap position figure 19. wiper digital feed-through figure 20. wiper transition glitch figure 21. wiper large signal settling time figure 22. power-on start-up in voltage divider mode typical performance curves (continued) 0 5 10 15 20 16 32 48 64 80 96 112 128 t c v ( p p m / c ) tap position (decimal) 100 110 120 130 140 150 16 32 48 64 80 96 112 128 tc r ( ppm / c ) tap position (decimal) 1s/div scl clock rw pi n 1v/div 10mv/div 20mv/div 5s/div 1v/div 1s/div scl 9th clock of the wiper data byte (ack) 1v/div 0.1s/div vrh = vcc vrw
isl23318 13 fn7887.0 july 26, 2011 functional pin descriptions potentiometers pins rh and rl the high (r h ) and low (r l ) terminals of the isl23318 are equivalent to the fixed terminals of a mechanical potentiometer. r h and r l are referenced to the relati ve position of the wiper and not the voltage potential on the terminals. with wr set to 127 decimal, the wiper will be closest to r h , and with the wr set to 0, the wiper is closest to r l . rw rw is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potent iometer. the position of the wiper within the array is determined by the wr register. bus interface pins serial data input/output (sda) the sda is a bidirectional serial data input/output pin for i 2 c interface. it receives device address, wiper address and data from an i 2 c external master device at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock. sda requires an external pull-up resistor, since it is an open drain input/output. serial clock (scl) this input is the serial clock of the i 2 c serial interface. scl requires an external pull-up resistor, since a master is an open drain output. device address (a1, a0) the address inputs are used to se t the least significant 2 bits of the 7-bit i 2 c interface slave address. a match in the slave address serial data stream must match with the address input pins in order to initiate communication with the isl23318. a maximum of four isl23318 devices may occupy the i 2 c serial bus (see table 3). v logic this is an input pin that supplies internal level translator for serial bus operation from 1.2v to 5.5v. principles of operation the isl23318 is an integrated ci rcuit incorporating one dcp with its associated registers and an i 2 c serial interface providing direct communication between a host and the potentiometer. the resistor array is comprised of individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operate in a ?make-before-break? mode when the wiper changes tap positions. voltage at any dcp pins, r h , r l or r w , should not exceed v cc level at any conditions during power-up and normal operation. the v logic pin needs to be connected to the i 2 c bus supply which allows reliable communic ation with the wide range of microcontrollers and independent of the v cc level. this is extremely important in systems where the master supply has lower levels than dcp analog supply. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. th e physical ends of each dcp are equivalent to the fixed terminals of a mechanical potentiometer (rh and rl pins). the rw pin of the dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by a 7-bit volatile wiper register (wr). when the wr of a dcp contains all zeroes (wr[7:0] = 00h), its wiper terminal (rw) is closest to its ?low? terminal (rl). when the wr regist er of a dcp contains all ones (wr[7:0] = 7fh), its wiper terminal (rw) is closest to its ?high? terminal (rh). as the value of th e wr increases from all zeroes (0) to 0111 1111b (127 decimal), the wiper moves figure 23. 10k -3db cut off frequency figure 24. standby current vs temperature typical performance curves (continued) r total = 10k -3db frequency = 1.4mhz at middle tap ch1: 0.5v/div, 0.2s/div rh pin ch2: 0.2v/div, 0.2s/div rw pin 0 0.2 0.4 0.6 0.8 1.0 1.2 -40 -15 10 35 60 85 110 s t a n d b y c u r r e n t i c c ( a ) temperature (c) v cc = 5.5v, v logic = 5.5v v cc = 1.7v, v logic = 1.2v
isl23318 14 fn7887.0 july 26, 2011 monotonically from the position closest to rl to the position closest to rh. at the same time, the resistance between rw and rl increases monotonically, while the resistance between rh and rw decreases monotonically. while the isl23318 is being powered up, the wr is reset to 40h (64 decimal), which locates rw roughly at the center between r l and r h . the wr can be read or writ ten to directly using the i 2 c serial interface as described in the following sections. memory description the isl23318 contains two volatile 8-bit registers: wiper register (wr) and access control register (acr). the memory map of isl23318 is shown in table 1. the wiper register (wr) at address 0 contains current wiper position. the access control register (acr) at address 10h contains information and control bits described in table 2. shutdown function the shdn bit (acr[6]) disables or enables shutdown mode for all dcp channels simultaneously. when th is bit is 0, i.e., dcp is forced to end-to-end open circuit and rw is connected to rl through a 2k ? serial resistor as shown in figure 25. default value of the shdn bit is 1 in the shutdown mode, the rw te rminal is shorted to the rl terminal with around 2k ? resistance as shown in figure 25. when the device enters shutdown, all current dcp wr settings are maintained. when the device exits shutdown, the wipers will return to the previous wr settings after a short settling time (see figure 26). in shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3v for more than 0.2s to 0.4s, the wipers will be reset to their mid position. this is done to avoid an undefined state at the wiper outputs. i 2 c serial interface the isl23318 supports an i 2 c bidirectional bus oriented protocol. the protocol defines an y device that sends data onto the bus as a transmitter and the re ceiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. th e master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl23318 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line must change only during scl low periods. sda state changes duri ng scl high are reserved for indicating start and stop conditions (see figure 27). on power-up of the isl23318, the sda pin is in the input mode. all i 2 c interface operations must be gin with a start condition, which is a high-to-low transition of sda while scl is high. the isl23318 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 27 ). a start condition is ignored during the power-up of the device. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 27). a stop condition at the end of a read operation or at the end of a write operation places the device in its standby mode. an ack (acknowledge) is a software convention used to indicate a successful data transfer. the tr ansmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 28). the isl23318 responds with an ack after recognition of a start condition followed by a valid iden tification byte, and once again table 1. memory map address (hex) volatile register name default setting (hex) 10 acr 40 0wr 40 table 2. access control register (acr) bit # 76543210 name/ value 0shdn 000000 figure 25. dcp connection in shutdown mode 2k ? rw rl rh figure 26. shutdown mode wiper response power-up user programmed mid scale = 80h shdn activated shdn released after shdn wiper voltage, v rw (v) shdn mode time (s) wiper restore to the original position 0
isl23318 15 fn7887.0 july 26, 2011 after successful receipt of an address byte. the isl23318 also responds with an ack after receiving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation. a valid identification byte contains 10100 as the five msbs, and the following two bits matching the logic values present at pins a1 and a0. the lsb is the read/write bit. its value is ?1? for a read operation and ?0? for a wr ite operation (see table 3). table 3. identification byte format 10100a1a0r/w (msb) (lsb) logic values at pins a1 and a0, respectively sda scl start data data stop stable change data stable figure 27. valid data changes, start and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 28. acknowledge response from receiver s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the slave a c k 10 1 00 a c k write signal at sda 000 a0 a1 figure 29. byte write sequence 0
isl23318 16 fn7887.0 july 26, 2011 write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the isl23318 responds with an ack. the data is transferred from i 2 c block to the corresponding register at the 9th clock of the data byte and device enters its standby state (see figures 28 and 29). read operation a read operation consists of a three byte instruction followed by one or more data bytes (see figure 30). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second iden tification byte with the r/w bit set to ?1?. after each of the three bytes, the isl23318 responds with an ack; then the isl23318 transmits data byte. the master terminates the read operation issuing a nack (ack ) and a stop condition following the last bit of the last data byte (see figure 30). applications information v logic requirements it is recommended to keep v logic powered all the time during normal operation. in a case where turning v logic off is necessary, it is recomme nded to ground the v logic pin of the isl23318. grounding the v logic pin or both v logic and v cc does not affect other devices on the same bus. it is good practice to put a 1f cap in parallel to 0.1f as close to the v logic pin as possible. v cc requirements and placement it is recommended to put a 1f capacitor in parallel with 0.1f decoupling capacitor close to the v cc pin. wiper transition when stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance ?make? to a much higher impedance ?break? within a short period of time (<1s). there are several code transitions such as 0fh to 10h, 1fh to 20h,..., 7eh to 7fh, which have higher transient glitch. note that all switching transients will settle we ll within the settling time as stated in the datasheet. a small capacitor can be added externally to reduce the amplit ude of these voltage transients. however, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. it may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 10 1 00 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 000 a0 a1 a0 a1 figure 30. read sequence a c k 0 0 101 0 read
isl23318 17 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7887.0 july 26, 2011 for additional products, see www.intersil.com/product_tree revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. products intersil corporation is a leader in the desi gn and manufacture of high-performance an alog semiconductors. the company's product s address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. in tersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl23318 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php date revision change 7/26/11 fn7887.0 initial release
isl23318 18 fn7887.0 july 26, 2011 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 0 12/02
isl23318 19 fn7887.0 july 26, 2011 package outline drawing l10.2.1x1.6a 10 lead ultra thin quad flat no-lead plastic package rev 5, 3/10 bottom view detail "x" side view typical recommended land pattern top view 1 2x 0.10 1.60 2.10 b a index area pin 1 1 (6x 0.50 ) (10 x 0.20) (0.10 min.) (0.05 min) 8. (10x 0.60) package (2.00) (0.80) (1.30) (2.50) 0.08 seating plane 0.10 c c c see detail "x" max. 0.55 0 . 125 ref 0-0.05 c 6 9 1 5 6x 0.50 c c 10 x 0.20 4 0.10 m ma b 0.80 pin #1 id 4 10 0.10 min. 0.05 min. 4x 0.20 min. 8. 10x 0.40 outline lead width dimension applies to the metallized terminal and is measured the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. dimensioning and tolerancing conform to asme y14.5m-1994. unless otherwise specified, tolerance : decimal 0.05 1. all dimensions are in millimeters. angles are in degrees. dimensions in ( ) for reference only. between 0.15mm and 0.30mm from the terminal tip. maximum package warpage is 0.05mm. 4. 5. 2. 3. notes: maximum allowable burrs is 0.076mm in all directions. 6. same as jedec mo-255uabd except: 7. no lead-pull-back, min. package thickness = 0.45 not 0.50mm lead length dim. = 0.45mm max. not 0.42mm. 8.

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